1. Field of the Invention
This invention relates generally to the manufacture of integrated-circuits, and more particularly to the manufacture of integrated-circuits using silicon-on-insulator (SOI) techniques.
2. Description of the Prior Art
Many studies have investigated the properties of silicon-on-insulator (SOI) integrated-circuit structures having a buried oxide layer formed by a deep, high-dose oxygen implantation. See, for example, Pinizzotto, et al., IEEE Trans. Nuclear Science NS-30, 1718 (1983); Wilson, Journal of Electronic Materials, 13, 127 (1984); and Hashimoto, et al., 1985 International Device Meeting Digest (Washington, D.C., Dec. 2-4, 1985), paper 28.1, p. 672. In most of the reported studies, including those cited above, the oxygen has been implanted prior to device processing so that the buried oxide extends under the entire transistor structure, producing a completely dielectrically isolated transistor.
SOI devices have a number of advantages over conventionally formed integrated-circuit devices, including reduced device/substrate capacitance, reduced leakage, and higher speed. However, SOI processing can add to the expense and manufacturing time of an integrated-circuit wafer and can cause operational problems with some types of integrated-circuit devices.
For example, when a MOS transistor having a source, channel, drain, and gate is formed entirely over an insulator, the neutral or body region under the channel is electrically isolated from the substrate and therefore "floats" with respect to the substrate potential. The floating-body of the MOS transistor can acquire a potential which can interfere with the proper functioning of the MOS transistor. Furthermore, the floating-body of a SOI MOS transistor often results in a degradation of the transient response of the transistor.
In a CMOS device an N-channel MOS transistor is coupled to a complementary P-channel MOS transistor to provide a device having very low power requirements. A problem which occurs with CMOS devices, however, is when current flows through the substrate between the complementary MOS transistors causing "latch-up" and possible destruction of the CMOS device. Dielectrically isolating the CMOS device from the substrate eliminates this problem, but introduces the aforementioned floating-body problem, particularly with respect to the N-channel MOS transistor, which is more sensitive than the P-channel MOS transistor to the floating-body effect.
The prior art does not disclose processes or structures which combine the best features of SOI and standard integrated-circuit processes and structures. More particularly the prior art does not disclose a method for implanting a buried oxide layer under selected portions of an integrated-circuit device to selectively isolate portions of the device from the underlying substrate while permitting other portions of the device to remain in electrical contact with the substrate, nor does it disclose structures having patterned, buried oxide layers.